System and method to reduce noise in a substrate

ABSTRACT

Disclosed herein is a system adapted to reduce noise in a substrate of a chip. The chip may include a substrate having a first well disposed there atop. The first well may be a deep well. A second well and a third may also be disposed within the first well. A first transistor may be disposed in the second well. A quiet voltage source may be connected to a body of the first transistor. A second transistor may be disposed in the third well. The first transistor may be a PMOS transistor and the second transistor may be an NMOS transistor. A noisy voltage source may be coupled to a source of the first transistor. A body of the first transistor may be resistively coupled to the second well.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of the following U.S. patent applications Ser. No. 10/294,880 filed on Nov. 14, 2002, Ser. No. 10/706,218 filed on Nov. 12, 2003, Ser. No. 10/801,260 filed on Mar. 15, 2004, and Ser. No. 10/801,290 filed on Mar. 15, 2004, all of which make reference to, claim priority to and claim the benefit of U.S. Provisional Patent Application Ser. No. 60/402,095 filed on Aug. 7, 2002.

All of the above stated applications are incorporated herein by reference in their respective entireties.

BACKGROUND OF THE INVENTION

As more and more functional blocks are added, for example, to a chip, an integrated circuit (IC), or an integrated system or device, the risk of generation and propagation of noise between different functional blocks, or within a functional block, may become quite substantial.

An exemplary conventional complementary metal oxide semiconductor (CMOS) transistor arrangement is illustrated in FIG. 1. As shown in FIG. 1, the conventional CMOS transistor arrangement 10 includes an n-channel MOS (NMOS) transistor 30 and a p-channel MOS (PMOS) transistor 40. The conventional CMOS arrangement 10 also includes a p-substrate 20 (e.g., a p⁻-substrate). The NMOS transistor 30 is disposed in the p-substrate 20. The NMOS transistor 30 includes a p⁺-body (B), an n⁺-source (S) and an n⁺-drain (D) disposed in the p-substrate 20. A voltage source V_(SS) 7 having a ground is coupled to the p⁺-body (B) and the n⁺-source (S) of NMOS transistor 30. An input line 5 is coupled to a gate (G) of the NMOS transistor 30. An output line 15 is coupled to the n⁺-drain (D) of the NMOS transistor 30. The PMOS transistor 40 includes an n-well 50 that is disposed in the p-substrate 20. The PMOS transistor 40 also includes an n⁺-body (B), a p⁺-source (S) and a p⁺-drain (D) disposed in the n-well 50. A voltage source V_(DD) 17 is coupled to the p⁺-source (S) and the n⁺-body (B) of PMOS transistor 50. The input line 5 is also coupled to a gate of the PMOS transistor 40. The output line 15 is also coupled to the p⁺-drain (D) of the PMOS transistor 40.

During normal operation of the conventional CMOS transistor arrangement 10, voltage sources V_(SS) 7 and V_(DD) 17 may be noisy. For example, noise may be caused by other circuitry found on or coupled to the chip that may directly or indirectly affect the voltage sources V_(SS) 7 and V_(DD) 17. High swing or high power devices, such as data drivers in a wire line communication system or transmitters in wireless communications systems, may be sources of noise. Noise may also be caused, for example, by the driving of active circuits. In one example, the voltage sources may be coupled to active circuitry (e.g., active portions of an inverter circuit) which may cause transient currents to flow during signal transitions from a high level to a low level or from a low level to a high level. In another example, noise may be caused by transitions in a signal propagated or generated by the chip.

In the NMOS transistor 30, if the voltage source V_(SS) 7 is noisy, then the noise may propagate to the p-substrate 20 via, for example, at least through the resistive coupling 9 between the p⁺-body (B) and the p-substrate 20. In the PMOS transistor 40, if the voltage source V_(DD) 17 is noisy, then the noise may propagate to the n-well 50 via the n⁺-body (B) of the PMOS transistor 40 via a resistive coupling 19. The noise in the n-well 50 may propagate to the p-substrate 20 via, for example, at least the capacitive coupling 29 between the n-well 50 and the p-substrate 20. If the noise is able to propagate to the p-substrate 20, then noise may propagate to or otherwise affect other circuits on or off the chip that may be coupled to the p-substrate 20.

FIG. 1A shows another conventional CMOS arrangement 10, which is similar to the conventional CMOS arrangement 10 shown in FIG. 1, except that a quieter voltage source V_(SS) 3 may be coupled to the p⁺-body (B) of the NMOS transistor 30 and a noisy voltage source V_(SS) 7 may be coupled to the n⁺-source (S) of the NMOS transistor 30. Thus, less noise is resistively coupled from the p⁺-body (B) to the p-substrate 20. To a lesser extent, noise may be capacitively coupled between the n⁺-source and the p-substrate 20. Noise may be coupled from the PMOS transistor 40 to the p-substrate 20, as described above with respect to the conventional CMOS arrangement 10, and as shown in FIG. 1. In the CMOS arrangement of FIG. 1A, noise may substantially propagate to the p-substrate 20. Accordingly, there is a need to mitigate noise in the substrate of a chip.

Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.

BRIEF SUMMARY OF THE INVENTION

Aspects of the present invention may be found in a system for reducing noise in a chip. The system may comprise a substrate doped with a first dopant and a first well doped with a second dopant. The first well may be disposed atop the substrate. A first transistor may be disposed in a second well and a second transistor may be disposed in a third well. The second well and the third well may be disposed within the first well.

In an embodiment according to the present invention, the first transistor may be a PMOS transistor.

In an embodiment according to the present invention, the second transistor may be an NMOS transistor.

In an embodiment according to the present invention, the system may further comprise a noisy voltage source coupled to a source of the first transistor.

In an embodiment according to the present invention, the system may further comprise a quiet voltage source coupled to a body of the first transistor.

In an embodiment according to the present invention, a body of the first transistor may be resistively coupled to the second well.

In an embodiment according to the present invention, the system may further comprise a noisy voltage source. A body and a source of the second transistor may both be coupled to the noisy voltage source.

In an embodiment according to the present invention, the body of the second transistor may be capacitively coupled to the substrate.

In an embodiment according to the present invention, the first well may be a deep well.

In an embodiment according to the present invention, the second well may be doped with the second dopant.

In an embodiment according to the present invention, the third well may be doped with the first dopant.

Aspects of the present invention may be found in a method for reducing noise in a chip. The method may comprise disposing a substrate layer within the chip, disposing a transistor layer within the chip, shielding the substrate layer from the transistor layer by disposing a shielding layer therebetween, and coupling the transistor layer to the shielding layer employing a first transistor type.

In an embodiment according to the present invention, the method may further comprise coupling a quiet voltage source to the first transistor type and coupling a second transistor type coupled to the shielding layer.

In an embodiment according to the present invention, the second transistor type may be an n-type transistor and the first transistor type may be a p-type transistor.

In an embodiment according to the present invention, the method may further comprise disposing the second transistor type within the transistor layer and resistively coupling the second transistor type to the shielding layer.

In an embodiment according to the present invention, the method may further comprise coupling a first noisy voltage source to a source of the second transistor type.

In an embodiment according to the present invention, the method may further comprise disposing the first transistor type within the transistor layer.

In an embodiment according to the present invention, the method may further comprise capacitively coupling the first transistor type to the shielding layer and capacitively coupling the shielding layer to the substrate layer.

In an embodiment according to the present invention, the shielding layer may be a deep N-well.

Certain embodiments of the present invention may be found in, for example, a system that reduces noise in a substrate of a chip. Aspects of the system may comprise a substrate and a first well disposed on top of the substrate. The first well may be a deep well. A second well and a third well may also both be disposed within the first well. A first transistor may be disposed in the second well. A quiet voltage source may be connected to a body of the first transistor and a second transistor may be disposed in the third well. The first transistor may be a PMOS transistor and the second transistor may be an NMOS transistor. A noisy voltage source may be coupled to a source of the first transistor. A body of the first transistor may be resistively coupled to the second well.

The system may further comprise a noisy voltage source, wherein a body and a source of the second transistor may both be coupled to the noisy voltage source. The body of the second transistor may be capacitively coupled to the substrate. The substrate and the third well may be doped with a first dopant, wherein the first well and the second well may also be doped with a second dopant.

These and other advantages, aspects and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIGS. 1 AND 1A show embodiments of conventional complementary metal oxide semiconductor (CMOS) transistor arrangements.

FIG. 2 shows an embodiment of a CMOS transistor arrangement according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2 shows an embodiment of a complementary metal oxide semiconductor (CMOS) transistor arrangement 60 in accordance with the present invention. The CMOS transistor arrangement 60 may include a p-substrate 70, a deep n-well 80, an n-channel MOS (NMOS) transistor 90, and a p-channel MOS (PMOS) transistor 100. The NMOS transistor 90 may include, for example, a p⁺-body (B), an n⁺-source (S), and an n⁺-drain (D), which may be disposed in a p-well 110. The p-well 110 may be an isolated p-well, for example, and may be disposed between two n-wells 120 and the deep n-well 80. A voltage source V_(SS) 170 having an electrical ground may be coupled to the p⁺-body (B) and the n⁺-source (S) of the NMOS transistor 90. An input signal line 150 may be coupled to a gate of the NMOS transistor 90. An output signal line 160 may be coupled to the n⁺-drain of the NMOS transistor 90.

The PMOS transistor 100 may include, for example, an n⁺-body (B), a p⁺-source (S), and a p⁺-drain (D), which may be disposed in an n-well 120. A first voltage source V_(DD) 130 may be coupled to the p⁺-source (S). A second voltage source V_(DD) 140 may be coupled to the n⁺-body (B) of the PMOS transistor 100. In an embodiment according to the present invention, the second voltage source V_(DD) 140 may be less noisy than the first voltage source V_(DD) 130. In this regard, V_(DD) 140 may be a quieter voltage source in comparison to the voltage source V_(DD) 130. The input signal line 150 may be coupled to a gate of the PMOS transistor 100. The output signal line 160 may be coupled to the p⁺-drain (D) of the PMOS transistor 100.

The voltage source V_(DD) 130 and the quieter voltage source V_(DD) 140 may be different voltage sources. The quieter voltage source V_(DD) 140 may be a dedicated voltage source that is not coupled to some sources of noise, for example, and may be an active component of a transistor. The quieter voltage source V_(DD) 140 may be dedicated, for example, to a guard bar for well taps or substrate taps. Alternatively, the voltage source V_(DD) 130 and the quieter voltage source V_(DD) 140 may be coupled to the same voltage source. However, the quieter voltage source V_(DD) 140 may be isolated or separated from the voltage source V_(DD) 130, wherein less noise may be carried by the quieter voltage source V_(DD) 140.

In operation, the voltage source V_(SS) 170 and the voltage source V_(DD) 130 may be noisy due to a number of factors, some of which are described herein. For example, noise may be caused by circuitry found on or coupled to the chip that may directly or indirectly affect the voltage sources V_(SS) 170 and/or V_(DD) 130. High swing or high power devices, such as data drivers in a wire line communication system or transmitters in wireless communications systems, may be sources of noise. Noise may also be caused, for example, by the driving of active circuits. In one example, the voltage sources may be coupled to active circuitry (e.g., active portions of an inverter circuit), which may cause transient currents to flow during signal transitions from a high level to a low level or from a low level to a high level. In another example, noise may be caused by transitions in a signal propagated or generated by the chip and/or associated circuitry.

In accordance with an inventive CMOS transistor arrangement 60, one source of noise is that the voltage sources V_(SS) 170 and/or V_(DD) 130 may be coupled to the sources of the NMOS transistor 90 and the PMOS transistor 100. Thus, for example, when the circuit is in a transitional state, such as during a signal transition from a high level to a low level or from a low level to a high level, a transient current may flow between the voltage sources V_(SS) 170 and/or V_(DD) 130. Notably, if other devices (e.g., other CMOS transistor arrangements) share the voltage sources V_(SS) 170 and/or V_(DD) 130, then the noise generated by the transient current flows may be substantial.

The noise in the voltage source V_(SS) 170 may flow into the body (B) and the source (S) of the NMOS transistor 90. The body (B) of the NMOS transistor 90 may be resistively coupled 180 to the p-well 110 and the source (S) of the NMOS transistor 90 may be capacitively coupled 190 to the p-well 110. The resistive coupling 180 may be much more substantial than the capacitive coupling 190. Accordingly, most of the noise in the p-well 110 may be associated with the p⁺-body of the NMOS transistor 90. For noise in the p-well 110 to reach the p-substrate 70, the noise may need to pass through two capacitive couplings: a capacitive coupling 200 between the p-well 110 and the deep n-well 80, and a capacitive coupling 210 between the deep n-well 80 and the p-substrate 70. Importantly, the capacitive coupling may generally be fairly weak, but the capacitive coupling may be even weaker when the couplings are placed in series. Thus, in an embodiment of the present invention, the resistive couplings 180, 200, and 210 between the p⁺-body (B) of the NMOS transistor 90 through to the p-substrate 70 may be replaced with a much weaker capacitive coupling.

The noise in voltage source V_(DD) 130 may flow into the p⁺-source (S) of the PMOS transistor 100. In this embodiment, the present invention may employ a quieter voltage source V_(DD) 140, which may be coupled to the n⁺-body (B) of the PMOS transistor 100. The p⁺-source (S) of the PMOS transistor 100 may be capacitively coupled 220 to the n-well 120 and the n⁺-body (B) of the PMOS transistor 100 may be resistively coupled 230 to the n-well 120. Because the resistive coupling 230 may be more substantial than the capacitive coupling, the noise in the n-well 120 may be mostly from the quieter voltage source V_(DD) 140. Advantageously, noise in the n-well 120 may be substantially reduced, by connecting the quieter voltage source V_(DD) 140 to the n⁺-body (B) of the PMOS transistor 100. The n-well 120 and the deep n-well 80 may be resistively coupled 240. Notably, the deep n-well 80 may provide a substantial amount of resistance to noise, thereby further reducing any noise propagating through PMOS resistor 100 and reaching substrate 70. The deep n-well 80 and the p-substrate 70 may be capacitively coupled, which may offer the noise only a weak coupling.

Although illustrated in use with a CMOS transistor arrangement, the present invention need not be so limited. The present invention may also be applicable for use with other types of transistors and/or other types of transistor arrangements. Notably, in an embodiment of the present invention, quiet voltage source V_(DD) may be used to replace a conventional voltage source V_(SS) without an area penalty. In this regard, the area used by voltage source V_(DD) may replace the area used by voltage source V_(SS), for example, in a block or standard resistor/transistor logic (RTL) arrangement. The present invention may also be applicable for use with other electrical, magnetic or electromagnetic components and/or circuits. Furthermore, although one or more of the embodiments described above may employ semiconductor materials (e.g., semiconductor material, compound semiconductor material, etc.), the present invention may also employ other materials (e.g., ceramics, metals, alloys, superconductors, etc.) and/or combinations thereof. In addition, the present invention may also contemplate employing different dopant types, dopant schemes, and/or dopant concentrations other than and/or in addition to the above-described dopant types, dopant schemes, and/or dopant concentrations.

While the present invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present invention without departing from its scope. Therefore, it is intended that the present invention not be limited to the particular embodiment disclosed, but that the present invention will include all embodiments falling within the scope of the appended claims. 

1. A system for reducing noise in a chip, the system comprising: a substrate doped with a first dopant; a first well doped with a second dopant, the first well disposed on top of the substrate; a first circuit disposed in a second well; and a second circuit disposed in a third well, wherein the second well and the third well are disposed within the first well.
 2. The system according to claim 1, wherein the first circuit comprises a first transistor, and the first transistor comprises a PMOS transistor.
 3. The system according to claim 2, further comprising a noisy voltage source coupled to a source of the first transistor.
 4. The system according to claim 2, further comprising a quiet voltage source connected to a body of the first transistor.
 5. The system according to claim 2, wherein a body of the first transistor is resistively coupled to the second well.
 6. The system according to claim 1, wherein the second circuit comprises a second transistor, and the second transistor comprises an NMOS transistor.
 7. The system according to claim 6, further comprising a noisy voltage source, wherein a body and a source of the second transistor are both coupled to the noisy voltage source.
 8. The system according to claim 6, wherein the body of the second transistor is capacitively coupled to the substrate.
 9. The system according to claim 1, wherein the first well is a deep well.
 10. The system according to claim 1, wherein the second well is doped with the second dopant.
 11. The system according to claim 1, wherein the third well is doped with the first dopant.
 12. A method for reducing noise in a chip, the method comprising: disposing a substrate layer within the chip; disposing a circuit layer within the chip; shielding the substrate layer from the circuit layer by disposing a shielding layer therebetween; and coupling the circuit layer to the shielding layer employing a first circuit.
 13. The method according to claim 12, wherein the first circuit comprises a first transistor, and the first transistor comprises a p-type transistor.
 14. The method according to claim 12, further comprising: coupling a quiet voltage source to the first circuit; and coupling a second circuit to the shielding layer.
 15. The method according to claim 14, wherein the second circuit comprises a second transistor, and the second transistor comprises an n-type transistor.
 16. The method according to claim 15, further comprising coupling a first noisy voltage source to a source of the second transistor.
 17. The method according to claim 14, further comprising: disposing the second circuit within the circuit layer; and resistively coupling the second circuit to the shielding layer.
 18. The method according to claim 12, further comprising disposing the first circuit within the circuit layer.
 19. The method according to claim 12, further comprising: capacitively coupling the first circuit to the shielding layer; and capacitively coupling the shielding layer to the substrate layer.
 20. The method according to claim 12, wherein the shielding layer comprises a deep N-well. 